Method and system for file system management using a flash-erasable, programmable, read-only memory
Microsoft Corp.This patent was asserted by Microsoft Corp. against TomTom
Summary / Description
| Summary / Description | US Patent 6904400 http://www.freepatentsonline.com/6904400.html Seem to cover many of the claims. |
Basic Information
| Type of Prior Art | Issued Patents - US |
| Country | United States of America |
| Patent/Application # | 6904400 |
| Kind Code | United States (US) - United STATES Patent - A |
| Patentee Name | STMicroelectronics S.r.l. (Agrate Brianza, IT) |
| Relevant Pages, Columns, or Lines | Representative Image, Claims |
| URL | http://www.freepatentsonline.c... |
| Publication Date | June 7, 2005 |
| Additional Information | |
Notes / To Do
| Notes | Flash emulation is noting really new. It's found in most mobile phones, as flash is cheaper than EEPROM. |
Excerpt
The Microsoft patent describes typical EEPROM Emulation and in combination with a flash file system. The EEPROM emulation part is covered by this patent. The file structure not.
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Claims
Storing and identifying data regions
A method of addressing a data region in a computer memory device, the memory divided into blocks, each block having a physical block number, the method comprising the steps of:
storing an allocation table in each block, the allocation table having entries that indicate an offset of a data region within the block and that have an entry index;
storing a logical block number in each block;
identifying a data region by logical block number and allocation table entry index; and
generating an address to the identified data region based on the logical block number and the allocation table entry index.
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21. An emulated EEPROM memory array comprising: a NOR flash memory array located on an integrated circuit, the NOR flash memory array being organized into a plurality of sectors for emulating EEPROM byte alterability a microcontroller coupled for controlling data access to and from an addressing of the flash memory array; an address counter whose output is coupled to an internal address bits of the memory array for tracking and controlling the address at which emulated EEPROM data is stored; and a state machine coupled to the address counter and coupled for outputting control signals, the address counter receiving control signals from the state machine to control the loading of hard coded addresses in storage registers which are read and updated by the microcontroller during a reset phase or by the state machine after an EEPROM update.
21. An emulated EEPROM memory array comprising: a NOR flash memory array located on an integrated circuit, the NOR flash memory array being organized into a plurality of sectors for emulating EEPROM byte alterability a microcontroller coupled for controlling data access to and from an addressing of the flash memory array; an address counter whose output is coupled to an internal address bits of the memory array for tracking and controlling the address at which emulated EEPROM data is stored; and a state machine coupled to the address counter and coupled for outputting control signals, the address counter receiving control signals from the state machine to control the loading of hard coded addresses in storage registers which are read and updated by the microcontroller during a reset phase or by the state machine after an EEPROM update.
Claim Chart
Some
Memory manager with file allocation table
A method of managing memory in a block-erasable, programmable, read-only memory, the memory being divided into blocks of memory locations, each block have a table and a data region divided into data areas, each table having entries corresponding to the data areas, the method comprising the steps of:
selecting a block in which to store data;
selecting a data area within the data region for the selected block in which to store data;
selecting a table entry to correspond to the selected data area;
setting the selected table entry to correspond to the selected data area and to indicate that the data area contains data; and
storing data in the selected data area.
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8. A method for emulating features of an EEPROM memory device incorporated into a memory macrocell which is embedded into an integrated circuit that also includes a microcontroller and a NOR Flash memory structure formed by a predetermined number of sectors, comprising using at least two sectors of the NOR Flash memory structure to emulate EEPROM byte alterability by dividing each of said at least two sectors into a predetermined number of blocks of the same size and each block into a pre-determined number of pages and updating the emulated EEPROM memory portion programming different memory locations in a single bit mode, wherein at a page update selected page data are moved to a next free block and, when an emulated EEPROM sector is full, all the pages are swapped to another emulated EEPROM sector.
8. A method for emulating features of an EEPROM memory device incorporated into a memory macrocell which is embedded into an integrated circuit that also includes a microcontroller and a NOR Flash memory structure formed by a predetermined number of sectors, comprising using at least two sectors of the NOR Flash memory structure to emulate EEPROM byte alterability by dividing each of said at least two sectors into a predetermined number of blocks of the same size and each block into a pre-determined number of pages and updating the emulated EEPROM memory portion programming different memory locations in a single bit mode, wherein at a page update selected page data are moved to a next free block and, when an emulated EEPROM sector is full, all the pages are swapped to another emulated EEPROM sector.
Claim Chart
Some
Memory manager with file allocation table
A manager for a computer memory comprising:
a block allocation routine, the memory divided into blocks of memory locations, each block having an allocation table and a data region divided into data areas, each allocation table having entries corresponding to region data areas, the block allocation routine for selecting a block in which to store data;
a data area allocation routine for selecting a data area within the data region for the selected block in which to store data, for selecting an allocation table entry to correspond to the selected data area, and for setting the selected allocation table entry to correspond to the selected data area and to an allocated state; and
a storage routine for storing data in the selected data area.
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1. An emulated EEPROM memory device, comprising; a memory macrocell which is embedded into an integrated circuit having a microcontroller, the memory macrocell including: a NOR Flash memory structure formed by a predetermined number of sectors, at least one sector of the NOR Flash memory structure having a selected number of NOR Flash memory cells that are structured to emulate EEPROM byte alterability corresponding to an EEPROM memory array having a selected number of EEPROM memory cells, the selected number of EEPROM memory cells being fewer than the selected number of NOR Flash memory cells.
5. The emulated EEPROM memory device according to claim 2, wherein hardware means includes a state machine for controlling an address counter which has an output connected to an internal
address bus running inside the memory macrocell, said address counter receiving control signals from the state machine in order to control the loading of hard-coded addresses in volatile or non-volatile registers which are read and updated by the microcontroller during a reset phase or by the state machine after an EEPROM update.
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1. An emulated EEPROM memory device, comprising; a memory macrocell which is embedded into an integrated circuit having a microcontroller, the memory macrocell including: a NOR Flash memory structure formed by a predetermined number of sectors, at least one sector of the NOR Flash memory structure having a selected number of NOR Flash memory cells that are structured to emulate EEPROM byte alterability corresponding to an EEPROM memory array having a selected number of EEPROM memory cells, the selected number of EEPROM memory cells being fewer than the selected number of NOR Flash memory cells.
5. The emulated EEPROM memory device according to claim 2, wherein hardware means includes a state machine for controlling an address counter which has an output connected to an internal
address bus running inside the memory macrocell, said address counter receiving control signals from the state machine in order to control the loading of hard-coded addresses in volatile or non-volatile registers which are read and updated by the microcontroller during a reset phase or by the state machine after an EEPROM update.
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Copying allocated data regions into continguous memory
The method of Claim 4 wherein the allocated data regions are copied into contiguous memory locations in the spare block.
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22. An emulated EEPROM memory array comprising: a NOR Flash memory array located on an integrated circuit, the NOR Flash memory array being organized into a plurality of sectors; a microcontroller coupled for controlling data access to and from an addressing of the flash memory array; an address counter whose output is coupled to an internal address bus of the memory array; and a state machine coupled to the address counter and coupled for outputting control signals the address counter receiving control signals from the state machine to control the loading of hard coded addresses in storage registers which are read and updated by the micro controller during a reset phase or by the state machine after an EEPROM update wherein said storage registers is a RAM buffer which is coupled for page updating of the EEPROM, the RAM buffer including sufficient storage for storing a page address of the memory array during a page update phase.
22. An emulated EEPROM memory array comprising: a NOR Flash memory array located on an integrated circuit, the NOR Flash memory array being organized into a plurality of sectors; a microcontroller coupled for controlling data access to and from an addressing of the flash memory array; an address counter whose output is coupled to an internal address bus of the memory array; and a state machine coupled to the address counter and coupled for outputting control signals the address counter receiving control signals from the state machine to control the loading of hard coded addresses in storage registers which are read and updated by the micro controller during a reset phase or by the state machine after an EEPROM update wherein said storage registers is a RAM buffer which is coupled for page updating of the EEPROM, the RAM buffer including sufficient storage for storing a page address of the memory array during a page update phase.
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Block-erasable, programmable ROM
The method of Claim 6 or 7 wherein the computer memory device is a block-erasable, programmable, read-only memory.
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1. An emulated EEPROM memory device, comprising; a memory macrocell which is embedded into an integrated circuit having a microcontroller, the memory macrocell including: a NOR Flash memory structure formed by a predetermined number of sectors, at least one sector of the NOR Flash memory structure having a selected number of NOR Flash memory cells that are structured to emulate EEPROM byte alterability corresponding to an EEPROM memory array having a selected number of EEPROM memory cells, the selected number of EEPROM memory cells being fewer than the selected number of NOR Flash memory cells.
17. ... in response to each write instruction requesting to write data to the selected page address ...
18. The method of claim 15, further comprising erasing the second memory sector while updating memory pages of the first memory sector.
19. The method of claim 18 wherein the erasing act is performed in plural erase phases, with each of the erase phases being triggered by writing data in the first memory sector.
1. An emulated EEPROM memory device, comprising; a memory macrocell which is embedded into an integrated circuit having a microcontroller, the memory macrocell including: a NOR Flash memory structure formed by a predetermined number of sectors, at least one sector of the NOR Flash memory structure having a selected number of NOR Flash memory cells that are structured to emulate EEPROM byte alterability corresponding to an EEPROM memory array having a selected number of EEPROM memory cells, the selected number of EEPROM memory cells being fewer than the selected number of NOR Flash memory cells.
17. ... in response to each write instruction requesting to write data to the selected page address ...
18. The method of claim 15, further comprising erasing the second memory sector while updating memory pages of the first memory sector.
19. The method of claim 18 wherein the erasing act is performed in plural erase phases, with each of the erase phases being triggered by writing data in the first memory sector.
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Reclaiming deallocated space
A method of reclaiming deallocated space in a block-eraseable, programmable, read-only memory, the memory having blocks, the method comprising the steps of:
identifying data regions as deallocated or allocated in a block to be reclaimed;
erasing a spare block; and
copying allocated data regions from the block to be reclaimed to the spare block whereby a memory area corresponding to the deallocated data region is reclaimed for allocation.
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18. The method of claim 15, further comprising erasing the second memory sector while updating memory pages of the first memory sector.
19. The method of claim 18 wherein the erasing act is performed in plural erase phases, with each of the erase phases being triggered by writing data in the first memory sector.
23. An emulated EEPROM memory comprising: a NOR flash memory array positioned on an integrated circuit, the NOR flash structure being of the type that permits simultaneous erasing of all cells in an entire sector but does not permit simultaneous erasing of less than all cells in a sector, at least two of the sectors being structured to emulate an EEPROM having byte erasability, the emulated EEPROM bytes comprising substantially fewer memory cells than an entire sector.
18. The method of claim 15, further comprising erasing the second memory sector while updating memory pages of the first memory sector.
19. The method of claim 18 wherein the erasing act is performed in plural erase phases, with each of the erase phases being triggered by writing data in the first memory sector.
23. An emulated EEPROM memory comprising: a NOR flash memory array positioned on an integrated circuit, the NOR flash structure being of the type that permits simultaneous erasing of all cells in an entire sector but does not permit simultaneous erasing of less than all cells in a sector, at least two of the sectors being structured to emulate an EEPROM having byte erasability, the emulated EEPROM bytes comprising substantially fewer memory cells than an entire sector.
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Generating data region addresses
The method of Claim 6 wherein the step of generating an address includes the steps of:
determining the physical block number from the logical block number, each block having a corresponding start address;
retrieving the offset from the allocation table entry in the determined physical block number that is indexed by the allocation table entry index; and
adding the retrieved offset to the start address of the block with the determined physical block number to generate the address of the identified data region.
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See previous.
See previous.
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Memory block reclamation
The manager for a computer memory of Claim 1 further comprising:
a data area deallocation routine for setting an allocation table entry that is in the allocated state to a deallocated state; and
a block reclamation routine for reclaiming data areas corresponding to allocation table entries that are in that deallocated state.
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A NOR Flash memory device for emulating an EEPROM, comprising: first and second NOR Flash memory portions each including plural memory blocks with plural memory locations, each of the memory locations sharing an address with a corresponding memory location in each of the blocks of the first and second NOR Flash memory portions, all of the memory locations sharing a same address being a set of memory locations; and a plurality of memory pointers each reflecting which memory block includes a current memory location for a set of memory locations, each set of memory locations including a current memory location; a memory controller structured to, in response to receiving a request to write data to a selected address assigned to a selected one of the sets of memory locations, determine from a memory pointer associated with the selected address which memory location in the selected set is a next memory location following the current memory location for the selected set and write the data in the next memory location; an internal address bus running inside the memory macrocell; an address counter having an output connected to the internal address bus; and a state machine for controlling the address counter, said address counter receiving control signals from the state machine in order to control the loading of hard-coded addresses such that the corresponding pages always share the same non-changeable address.
A NOR Flash memory device for emulating an EEPROM, comprising: first and second NOR Flash memory portions each including plural memory blocks with plural memory locations, each of the memory locations sharing an address with a corresponding memory location in each of the blocks of the first and second NOR Flash memory portions, all of the memory locations sharing a same address being a set of memory locations; and a plurality of memory pointers each reflecting which memory block includes a current memory location for a set of memory locations, each set of memory locations including a current memory location; a memory controller structured to, in response to receiving a request to write data to a selected address assigned to a selected one of the sets of memory locations, determine from a memory pointer associated with the selected address which memory location in the selected set is a next memory location following the current memory location for the selected set and write the data in the next memory location; an internal address bus running inside the memory macrocell; an address counter having an output connected to the internal address bus; and a state machine for controlling the address counter, said address counter receiving control signals from the state machine in order to control the loading of hard-coded addresses such that the corresponding pages always share the same non-changeable address.
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