TRACKBACKS

COMMENTS

1. Arne Jonsson, April 29th, 2009 at 08:33 AM
   Isn't this was JFFS was all about?
2. Rick Jafrate, April 30th, 2009 at 07:50 AM
   General Electric, Salem Virginia, shipped a product called DMC, (Distributed Micro Controller) from 1980-1990 as part of their control systems. Application software in the form of Relay Ladder Logic (and ASM86 modules) was developed under VAX/VMS, using in house programming tools, and downloaded to target DMCs, where it was stored in EEPROM memory. By 1992 DMCs were obsolete and replaced by GE's next generation platform.
   
   GE has exceptionally long support for spare parts etc. so it should be possible to obtain more information/documentation from them. HMHA is a generic memory board that can be populated with RAM or EEPROM memory chips. The board populated with EEPROM chips I believe has a designation of EEPA perhaps with a DS3800 prefix.
   
   I could also probably locate schematic drawings of this board at one of my client's sites. I would also be willing to make a statement about my knowledge of this item.
   
   Hope this is relevant.
   
   RickJ
   
3. Chris, April 30th, 2009 at 12:58 PM
   This one seems relevant - it's above my head, but sounds vaguely like JFFS:
   Abstract of GB 2243230 (A) [23 Oct 1991]
   For writing data into the memory regions of an EEPROM 40 a predetermined number of times, the data are written into the memory regions of which serial addresses are arranged to wrap around
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   This one discloses the allocation of bad blocks to a table:
   Abstract of EP 0424191 (A2) [24 April 1991]
   A solid-state memory array such as an EEprom or Flash EEprom array is used to store sequential data in a prescribed order. The memory includes a first information list containing addresses and defect types of previously detected defects.
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   This one discloses the concept of reducing the number of write operations:
   Abstract of JP 3220621 (A) [27 September 1991]
   PURPOSE:To reduce the number of times of the input/output of a disk device by forming a file control table and an input/output buffer on a non-volatile memory backed up with a backup power source.
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   This seems relevant:
   Abstract of JP 3250498 (A) [8 Nov 1991]
   PURPOSE:To make it possible to repeat data rewriting operation by several-ten times the performance of an EEPROM by dividing the contents of the EEPROM into N pages to manage the contents.
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   This discusses tracking the number of writes:
   Abstract of EP 0438050 (A2) [24 July 1991]
   An EPROM integrated circuit (20) includes a plurality of banks. When a data write operation is to be performed for this EEPROM integrated circuit (20), a bank which is used once is not used again, but the operation is constantly performed for new banks. In order to select a bank, a write number storage area (21) is provided in the EPROM integrated circuit (20), and the contents of the write number storage area (21) are updated by a write number updating circuit (29) each time the write operation is performed for a new bank.
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4. Greg Bishop, April 30th, 2009 at 02:14 PM
   This is no different really from flash ROM chips used to hold programs for the video games we used at KSE back in the early 90's, that were themselves based on earlier designs. Flash has improved (in that you don't have to put it under a UV light to erase it or use a eprom emulator), but the overall process is the same. There is nothing new here to justify a patent.
5. C. Lingo, May 14th, 2009 at 03:46 PM
   Commodore used an EEPROM for OS storage in the computers.

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